1. Field of the Invention
This invention relates to integrated circuit semiconductor chips and in particular, to the repair of defective interconnection lines, semiconductor dies and/or subassemblies and improvement of the engineering design of the packaging device. Specifically, the invention relates to a repairable multi-level overlay wiring system for a multi-level integrated packaging structure.
2. Prior Art
A variety of packaging structures for mounting integrated circuit chips on substrates are known in the art. One common technique utilizes mounting of integrated circuit chips onto substrates which carry film or printed circuits. In some situations, the integrated circuit chip is mounted face upward, with the array of connection contact areas uppermost such that connection between the contact areas and the jumper lands on the substrate is made by thin jumper wires extending over the edges of the chip. This technique is shown in U.S. Pat. No. 3,082,327. The converse situation is also employed where the chip is mounted face downward and its contact areas are bonded to conductor lands on the substrate. This is shown in U.S. Pat. No. 3,292,240.
Multi-level overlay wiring systems are also used for mounting semiconductor chips. These systems employ a plurality of layers for power distribution, a plurality of layers for chip-to-chip connections, and a plurality of layers for intrachip connections. A composite package comprising a number of discrete wiring layers is generally known as a multi-layer ceramic (MLC). Defects in the conductors in some of the layers are generally repaired by means of socalled engineering changes in the semiconductor packages. These engineering changes (EC) have, in the past, employed complex techniques to make connections involving the use of discrete wires on various surfaces of the ceramic from an EC pad to the conductor in question. Such changes have been made by the use of fly wires which in practice are difficult to use given the dimensional constraints of the system. In extreme situations the MLC is unrepairable since the defect may not be circumvented.
As VLSI circuit dimensions tend to decrease with increased packing density, the removal of insulation from the ends of fly wires becomes an inefficient technique in terms of fabrication labor costs and the propensity of operator error tending to damage or render useless the MLC. Moreover, the technique is labor intensive requiring discrete soldering from point to point as the EC is made. Hence, the use of fly wires is not cost effective.
Another problem as circuit dimensions tend to decrease is the technique of joining the contact areas of the chip to the respective conductor lands or printed wires forming a multi-layer circuit. The chip itself includes a solid state device having a plurality of separate or structural integrated resistors, diodes, resistors and capacitors formed in the monolithic body of the semiconductor material which must be protected during the joining operation. The integrated circuit cannot readily be isolated from the conductor for couplings forming the I/O to the chip. Various packaging structures have been proposed in the prior art to provide the necessary cooling, thermal and mechanical shock resistance to this integrated circuit while at the same time providing sufficient reliability of any conductor coupling.
The state of the prior art with respect to such integrated circuit packaging structures is typified by the following representative prior art considered, vis-a-vis the problem solved by the present invention.
U.S. Pat. No. 3,325,882 relates to a method of interconnecting metal lands located on an insulating substrate to selected metal lands located on the solid state device. The method perceives the use of a removable powdered material in a cavity space disposed about the solid state device. This permits a bridging metal interconnection to be made between the solid state device and the substrate.
A different technique is shown in U.S. Pat. No. 3,614,832. In this prior art patent, a plurality of connections from electrically conductive lands on an insulating substrate to the contacts of a solid state device are formed in one operation by using a decal including a backing plate with a plurality of conductive strips which can be adhered to the plate by means of a soluble adhesive. The decal is positioned over a substrate to which the solid state device has been positioned with the strips in registration with respective contacts and lands. The strips are brought into contact with respective contact and land surface portions and then subjected to heat and pressure treatment so that bonding between the strips and land surface portions occurs. Then, the decal backing plate may be removed from the strips, for example, by dissolving the adhesive thereby leaving the strips firmly bonded to the contacts and lands bridging the space therebetween.
U.S. Pat. No. 3,605,063 relates to a system for interconnecting electrical components although not of VLSI size. In accordance with this invention, printed circuit cards are used having individual electrical components mounted on the edge with electrical interconnection between the cards achieved using wiring cards of a specific design sandwiched between the component cards. Each of the component and wiring cards have on one side a plurality of paired and electrically connected conductive pads arranged in a matrix. One pad of each pair of pads is provided with a plated through hole to the other side of the card to a similar pad on that side. In the case of component cards, each pad pair is electrically isolated from the other pair and conductive paths connect the leads of the component to selected pad pairs. Different types of wiring cards are used to establish either vertical or horizontal conductive paths.
U.S. Pat. No. 3,662,230 relates to a interconnection system utilizing conductive patterns bonded to thin flexible insulating films. A packaging system as disclosed in that patent employs one or more semiconductor chips each having metal contact pads on at least one face. A rigid support is provided for the semiconductor chip and also large leads are used to connect the package device to an external circuit. Thin metallic film strips are bonded to a thin flexible dielectric sheet for support. The set of metal strips interconnects the contact paths of the semiconductor chips and selected leads to electrically interconnect the semiconductor device and the leads. If a plurality of semiconductor devices are used, a plurality of dielectric sheets are stacked with electrical connections made between the different layers of metal film strips through openings in the dielectric sheets.
U.S. Pat. No. 3,702,025 defines a system of interconnecting circuits on a substrate in a discretionary manner by first probing cells that are mounted on the substrate to determine which are defective or inoperative. The cells are covered by a dielectric layer, a second layer connection pattern is then formed and connections are made to contacts on only the good cells with the connection patterns skipping across defective cells.
U.S. Pat. No. 3,757,175 relates to a system of coplanar connections to semiconductor chips mounted on a single substrate by using a rigid dielectric substrate for supporting a number of semiconductor chips. The chips have metallized contact electrodes and an insulating material overlies one surface of the substrate in which the chips are embedded. The substrate has conductor strips with terminal electrodes to be used for connecting the contact electrodes. The chips are bonded to the substrate with the contact electrodes in registration with the terminal electrodes and with the contact and terminal electrodes contiguous with the surface of the insulating material. Metallization is then deposited on the surface of the insulating material extending between the contact and terminal electrodes to form electrical connections to the chips.
U.S. Pat. No. 3,780,352 also relates to a semiconductor interconnecting system utilizing conductive patterns bonded to thin flexible insulating films. In this patent, a packaging system for a plurality of semiconductor chips each having metal contact pads on at least one face is disclosed. A rigid support is provided for the chips and also for a series of leads which are used to connect the package device to an external circuit. Thin metallic film strips are bonded to a thin flexible dielectric sheet for support. The metal strips in the form of sets then interconnect the contact pads on the semiconductor chips to selected leads and thereby establish electrical interconnections of the semiconductor device and the leads. A plurality of dielectric sheets can be stacked and interconnections then made between different layers of thin metal strips through openings in the dielectric sheets if couplings to a plurality of semiconductor devices are to be established.
U.S. Pat. No. 3,781,596 also deals with packaging of semiconductors by means of flexible carriers. In this patent, the carrier comprises a film base having a pattern of discretionary conductors and bonding pads. The film acts as a supporting layer for the conductor pattern which itself is applied to one surface by selective deposition or etching of coatings in raised contact areas. The semiconductor chips are mounted so that the active chip surface is bonded to the carrier pads. Thereafter, the chip is connected to the circuitry of the substrate by the discretionary carrier conductor pattern. The carrier pads serve to provide discrete bonding areas for reliable bonding and prevent shorting by raising the carrier conductors of the active surface of the chip.
U.S. Pat. No. 3,978,578 relates to packaging of semiconductor devices utilizing a polyimide film with selected areas etched from the surface of the wafer. The etching exposes electrical contact areas of each of the semiconductor devices. The integrated circuit devices are then separated from the wafer and attached to a support. Electrical continuity is established by using bonding wires to couple the contact areas on each of the device with electrical conductors. The device is then coated with a second layer of polyimide film.
U.S. Pat. No. 4,072,982 discloses a semiconductor circuit having a plurality of plate-shaped semiconductor islands supported on a dielectric carrier. Doping layers are provided on the island and thin film deposits on selected areas of the dielectric carrier are used to interconnect selected islands.
U.S. Pat. No. 4,251,852, an invention by the same inventors herein, relates to a packaging structure for integrated circuits wherein a plurality of circuit chips are mounted on a number of membrane-like insulating members. Each of the membrane-like members provide multi-level wiring and interconnections between the chip or chips and a secondary wiring structure. The insulating membrane is material such as polyimide or parylene and by photoresist and etching procedures a number of openings in the membrane are provided over an active area of a particular chip such that by subsequent masking and metal deposition steps, metallic lands are provided to form electrical paths between the openings over a chip and openings for a secondary structure contact grid. A second thin layer of membrane material is then provided over the metallization of the first layer and is similarly processed to provide an identical set of openings in the secondary grid structure for a second chip. Accordingly, the interconnection of two memory chips to a common set of contact openings with levels of metal lands insulated from each other is accomplished such that the contact openings in both levels conform to a predetermined format.
U.S. Pat. No. 4,254,445 relates to an EC repair of VLSI devices. An array of chips are mounted on a substrate such that about each chip area a large peripheral area is defined for EC pads and for testing. Prefabricated thin film interconnection EC lines of varying lengths are preformed in the rows and columns between the peripheral areas surrounding each of the chips. These printed wire EC lines and pads are designed to have different lengths and are laid out so that the EC pads for different chips can be interconnected at the discretion of the designer. The '445 patent perceives a general hierarchy of EC lines having a multi-tier of long vertical lines of parallel shorter lines, a series of horizontal lines and fly wire interconnections. This hierarchy uses a generally orthogonal structure such that fly wire connections are extremely short.
In other prior art generally considered to define the background of this invention includes IBM Technical Disclosure Bulletins: Vol. 11, No. 3, August, 1968, pp. 309-310; Vol. 14, No. 10, March, 1972, p. 3090; Vol. 16, No. 3, August, 1973, p. 758; Vol. 18, No. 11, April, 1976, p. 3591; Vol. 21, No. 2, July, 1978, pp. 569-573; Vol. 21, No. 11, April, 1979, p. 4425; and Vol. 22, No. 11, April, 1980, pp. 4852-4854.
While the prior art is replete with a number of techniques for accomplishing engineering changes on various levels, none are believed to have specific application for a multi-layer ceramic (MLC) structure. In the context of such a complex semiconductor device, engineering change requirements may exist at different tier levels. For example, change may be required on a single chip carrier or, at a second level on a first tier carrier for an array of chips. A third level of engineering change may be required on a multi-chip carrier wherein each tier forms one block of a multi-chip array. Accordingly, a requirement exists for defining a system of multi-level engineering change capability to any electrical signal path terminating on, for example, an encapsulated chip, a tape automated bond chip carrier, leadless chip carrier and a face bonded chip.